This invention relates to a structure of a semiconductor integrated circuit and more particularly, to a structure of a vertical PNP transistor whose "withstand voltage" has conventionally been low. The term "withstand voltage" is defined for purposes herein as the maximum voltage at the collector relative to the substrate which does not create a state of punchthrough between the collector and the substrate of the integrated circuit.
A semiconductor integrated circuit is generally fabricated by the steps of forming an N-type silicon epitaxial layer on a P-type silicon substrate by vapor deposition techniques, dividing this N-type silicon epitaxial layer into plural island regions electrically isolated from one another by a P-type isolation region and forming transistors and resistors in the island regions. An NPN transistor is easy to fabricate in the N-type island region, with excellent electric characteristics, because its base and emitter can be formed by effecting impurity diffusion twice, but a PNP transistor is not so easy to fabricate.
The so-called lateral PNP transistor and vertical PNP transistor are known as the PNP structures for use in the semiconductor integrated circuit. The lateral PNP transistor is disclosed in U.S. Pat. No. 3,197,710 granted to H. C. Lin and is fabricated by forming two P-type regions spaced apart from each other in the lateral direction in one island region of an N-type epitaxial layer, wherein the P-type regions are used as the emitter and collector, respectively, with the N-type epitaxial layer as the base. The lateral PNP transistor of this type is extremely simple to fabricate but has the disadvantages that the current gain (h.sub.FE) is extremely small as compared with that of the ordinary NPN transistor, and the gain bandwidth product (f.sub.T) is low, and a current is likely to flow through the substrate due to parasitic current effects.
A vertical PNP transistor improves upon the above-mentioned drawbacks. A vertcial PNP transistor is disclosed in U.S. Pat. No. 3,702,428 granted to A. Schmitz. According to this prior art, an N.sup.+ buried layer and a P.sup.+ buried layer are sequentially formed on a P-type silicon substrate and an N-type epitaxial layer is further formed thereon. In this instance, each buried layer extends into the N-type epitaxial layer by diffusion. Thereafter, a close-loop or an annular encompassing P-type region which will serve as a collector in cooperation with the P.sup.+ buried layer is formed on the N-type epitaxial layer by diffusion techniques. The term annular region is used hereinafter to mean a region encompassing a closed loop and enclosing a region within the closed loop. At the same time, a P.sup.+ -type isolation region is formed together with the annular P-type region, so as to reach the P-type silicon substrate and thus to isolate the N-type epitaxial layer into plural island regions. The annular P.sup.+ -type region which is to serve as the collector is allowed to reach the extending portion of the P-type buried layer, thereby isolating the N-type epitaxial layer on the P.sup.+ -type buried region from the other portions. Thereafter, a P-type region, to serve as an emitter, is diffused into the N-type epitaxial layer on the P-type buried layer. The N-type epitaxial layer on the P-type buried layer serves as the base.
In the abovementioned vertical PNP transistor, the minor carriers which are injected from the emitter to the base and arrive at the collector are more than those in a lateral PNP transistor so that the current gain is greater than that in a lateral PNP transistor. Furthermore, since the base width can be reduced in comparison with that in a lateral PNP transistor, the gain bandwidth product (f.sub.T) can also be increased. However, the vertical PNP transistor is not devoid of problems in that the structure is complicated and the area occupied by the element is great. The area occupied by the element can be reduced only at the expense of the "withstand voltage" between the collector and the P-type substrate.
Next, the relation between the area occupied by the transistor element and the "withstand voltage" between the collector and the P-type substrate will be described.
In the vertical PNP transistor, the impurity concentration of the base is lower than that of the collector so that the depletion layer at the base-collector junction extends towards the base region. In order to sufficiently increase the base-collector withstand voltage, therefore, the base width must be sufficiently increased, but this results in an increase in the width of the N-type epitaxial layer. In order to form the P-type isolation region and the annular P-type region in such a manner as to reach the P-type substrate or the extending portion of the P.sup.+ -type buried layer through this thick N-type epitaxial layer, providing impurity diffusion in a high concentration for an extended period of time is inevitable. Accordingly, expansion in the lateral direction becomes greater on the surfaces of the P-type isolation region and the annular P.sup.+ -type region and they would come into contact with each other unless a sufficient gap is provided in advance. When each buried layer extends into the N-type epitaxial layer, it does not swell up straight but slants considerably. Hence, this direction of swelling direction must be taken into account in separating the P.sup.+ -type isolation region from the P.sup.+ -type buried layer, otherwise they would come into contact with each other and the collector would become conductive with the P-type substrate.
In order to avoid possible contact between each region, the gap must be provided to be sufficiently great between the P.sup.+ -type isolation region and the annular P.sup.+ -type region. This results in a large area occupied by the transistor element. In order to avoid contact of each region and at the same time to reduce the occupying area of the element, the withstand voltage between the collector and the substrate must be sacrificed. In other words, the gap between the P.sup.+ -type isolation region and the annular P.sup.+ -type region must, be as narrow as possible and the gap between the P.sup.+ -type isolation region and the P.sup.+ -type buried region must also be as narrow as possible. In this instance, the depletion layer of the PN junction between the annular P.sup.+ -type region and the N-type epitaxial layer around the outer circumference of the former expands into the N-type epitaxial layer. Since the impurity concentration of the N-type epitaxial layer is low, the depletion layer reaches the P.sup.+ -type isolation region at a low collector voltage, the result being occurrence of punch-through between the annular P.sup.+ -type region and P.sup.+ -type isolation region.
Thus, inspite of its advantage of a great current gain, the conventional vertical PNP transistor inherently involves the drawback that it occupies a large area and the withstand voltage between the collector and the substrate is low.